This invention relates to a random access read/write memory system and, more particularly, to a high density integrated circuit memory system requiring a minimum number of signal carrying conductors so as to enable denser packaging of the memory system.
A decrease in the number of signal lines that are deposited on the surface of an integrated circuit will provide an increase in the space that can be filled with circuits. If the circuits used are memory elements, then an increase in the bit density of an integrated memory system can be increased. In turn, the cost per bit will decrease due to the more efficient utilization of both materials and space.
The advantages associated with the reduction in the number of signal lines on an integrated circuit chip have been appreciated by inventors as evidenced by the following patents: In U.S. Pat. No. 3,691,538 entitled "Serial Read-Out Memory System," by R. B. Haney there is utilized a serial-by-bit address signal to minimize the number of address lines and, in addition, to provide a serial-by-bit output signal, again in order to eliminate signal conductors.
In U.S. Pat. No. 3,786,277, entitled "Circuit Arrangement of MOS Transistors Operating According to the Dynamic Principle for Decoding the Addresses for an MOS Memory," by Basse, there is disclosed a circuit wherein a single pin connection per MOS chip is used for receiving clock pulses. The one pin connection is utilized in conjunction with control pulses, which control pulses may be clock pulses, to provide a decoding circuit.
In U.S. Pat. No. 3,975,714 entitled "Data Processing System Including an LSI Chip Containing A Memory And Its Own Address Register", by G. Weber, there is disclosed a device wherein the number of connecting contacts is minimized by dividing the address bits into groups so that the number of lines necessary to parallel receive the total number of address bits is reduced. By eliminating a number of address lines, and accordingly a number of connecting conductors on the chips, savings are made in chip space.
In U.S. Pat. No. 4,007,452, entitled "Wafer Scale Integration System," by Hoff, Jr., the wafer surface area available for electronic circuitry is increased by eliminating the scribe lines and bonding pads which are used when the wafer has to be broken along scribe lines to form individual chips. It has been appreciated that if an entire wafer were utilized for electronic circuitry that a more efficient, cheaper and generally more reliable system could be formed.
U.S. Pat. No. 4,044,339 entitled "Block Oriented Random Access Memory," by R. O. Berg, describes a memory system wherein sequential addressing of each word of a memory block is undertaken in order to achieve a reduction in the number of input pins, and a corresponding reduction in the active chip area dedicated to the signal conductors associated with the pins. In addition, the patent directs itself to saving additional chip area by replacing a buffer and word decoder with a shift register.